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rev. 4572g?dect?01/04 features supply-voltage range 3 v to 4.6 v (regulated) auxiliary voltage regulator on-chip (3.2 v to 4.6 v) low current consumption few low-cost external components no mechanical tuning required supports multiple reference clocks (10.368 mhz/13.824 mhz) fast settling synthesizer (864 khz channel spacing) tx preamplifier with 3 dbm output power at 2.45 ghz (4 programmable power levels) ramp-signal generator for power ramping and power control of external sige power amplifier (t7024 and t7026) electrostatic sensitive device. observe precautions for handling. description the t2803 is an rf ic for low-power applications in the 2.45 ghz ism band. the qfn48-packaged ic is a complete transceiver including image rejection mixer, if amplifier, fm demodulator, baseband filter, rssi, tx preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated vco and gaus- sian data filter for tx. no mechanical tuning is necessary in production. figure 1. block diagram tank pc rc gf cp vco f : n f : n ctrl logic pd tx/rx switch ir mixer if amp 1 if amp 2 demod bb filter 3-wire bus demod dac rssi tx driver clock data enable rx_on tx_on pu_rx/tx pu_pll tx_data rssi bb_out cf demod if_tank if_in mixer out rf_in tx_out vs_vco cp ld ref_clk vtune vreg vs_reg reg_ctrl vreg_vco vco reg ramp gen ramp_out ramp_set aux reg ole pu_reg gnd_vco d/a i_cpsw ramp d/a 2.4 ghz wdect/ism single-chip transceiver t2803 preliminary
2 t2803 [preliminary] 4572g?dect?01/04 table 1. functional block description pin configuration figure 2. pinning qfn48 name description aux reg auxiliary voltage regulator bbf baseband filter cp charge pump dac d/a converter for demodulator tuning demod demodulator gf gaussian filter for transmit data if amp1 1st intermediate frequency amplifier if amp2 2nd intermediate frequency amplifier ir mixer image rejection mixer pc programmable counter pd phase detector ramp gen ramp-signal generator rc reference counter rssi received signal-strength indicator tx driver buffer amplifier for tx_out tx/rx switch switches vco signal to ir mixer respectively tx driver vco voltage-controlled oscillator vco reg voltage regulator for vco clock data enable ref_clk ld pu_reg vs_pll vreg reg_ctrl vs_reg gnd_cp vs_cp ramp_out if_in2 if_in1 vs_if tx_out gnd3 rf_in2 rf_in1 gnd2 if_tank2 if_tank1 rssi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 t2803 r x _ o n t x _ o n m i x e r _ o u t 1 o l e t x _ d a t a v s _ m i x e r g n d _ p l l p u _ r x / t x p u _ p l l i _ c p s w r a m p _ s e t m i x e r _ o u t 2 c p g n d _ v c o v s _ v c o g n d 1 v t u n e v r e g _ v c o b b _ o u t d a c _ d e c b b _ c f r e g _ d e c d e m o d _ t a n k 2 d e m o d _ t a n k 1
3 t2803 [preliminary] 4572g?dect?01/04 pin description pin symbol function configuration 1 2 3 clock data enable 3-wire-bus: clock input 3-wire-bus: data input 3-wire-bus: enable input 4 ref_clk reference-frequency input 5 ld lock-detect output 6 pu_reg power-up input for auxiliary voltage regulator clock data enable 1,2,3 5k 5k vs_pll 7 gnd_pll 43 vs_pll 7 ref_clk 4 10k gnd_pll 43 10k gnd_pll 43 100 ld 5 pu_reg 6 25k 25k gnd_pll 43
4 t2803 [preliminary] 4572g?dect?01/04 7 vs_pll pll supply voltage 8 9 10 vreg reg_ctrl vs_reg auxiliary voltage-regulator output auxiliary voltage-regulator control output auxiliary voltage-regulator supply voltage 11 12 13 gnd_cp vs_cp cp charge-pump ground charge-pump supply voltage charge-pump output pin description (continued) pin symbol function configuration gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 vreg 8 reg_ctrl 9 vs_reg 10 gnd_pll 43 vs_pll 7 vs_cp 12 cp 13 gnd_cp 11 vs_pll 7 gnd_pll 43
5 t2803 [preliminary] 4572g?dect?01/04 14 15 16 vs_vco vreg_vco gnd_vco vco voltage-regulator supply voltage vco voltage-regulator control output vco ground 17 vtune vco tuning voltage input 18 gnd1 ground pin description (continued) pin symbol function configuration vs_vco 14 gnd_vco 16 vreg_vco 15 vs_pll 7 gnd_pll 43 vtune 17 gnd_vco 16 vreg_vco 15 vs_pll 7 gnd_pll 43 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7
6 t2803 [preliminary] 4572g?dect?01/04 19 20 demod_tank1 demod_tank2 demodulator tank circuit demodulator tank circuit 21 dac_dec decoupling pin 22 reg_dec decoupling pin for vco_reg pin description (continued) pin symbol function configuration demod tank1 19 10k 10k demod tank2 20 vs_mixer 42 gnd1 18 vs_if 33 gnd2 28 dac_dec 21 10k gnd_vco 16 400 vreg_vco 15 vs_pll 7 gnd_pll 43 reg_dec 22 42k 2k vreg_vco 15 gnd_vco 16 vs_if 33 gnd2 28
7 t2803 [preliminary] 4572g?dect?01/04 23 bb_cf baseband filter corner-frequency control input 24 bb_out baseband filter output 25 rssi received signal strength indicator output 26 27 if_tank1 if_tank2 if tank circuit if tank circuit pin description (continued) pin symbol function configuration bb_cf 23 vs_if 33 gnd1 18 gnd2 28 vs_if 33 gnd1 18 bb_out 24 gnd2 28 vs_if 33 rssi 25 13k gnd2 28 if_tank1 26 vs_if 33 27 gnd2 28
8 t2803 [preliminary] 4572g?dect?01/04 28 gnd2 ground 29 30 rf_in1 rf_in2 rf input of image reject mixer rf input of image reject mixer 31 gnd3 ground pin description (continued) pin symbol function configuration gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 rf_in1 29 gnd2 28 vs_mixer 42 rf_in2 30 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7
9 t2803 [preliminary] 4572g?dect?01/04 32 tx_out tx driver amplifier output for pa 33 vs_if if amplifier supply voltage 34 35 if_in1 if_in2 if input of if amplifier if input of if amplifier 36 ramp_out ramp-generator output for pa power ramping pin description (continued) pin symbol function configuration tx_out 32 gnd3 31 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 if_in1 34 if_in2 35 90k vs_if 33 gnd2 28 vs_mixer 42 gnd2 28 ramp_out 36 vs_if 33
10 t2803 [preliminary] 4572g?dect?01/04 37 ramp_set slew-rate setting of ramping signal 38 39 rx_on tx_on rx control input tx control input 40 41 mixer_out1 mixer_out2 mixer output to saw filter mixer output to saw filter pin description (continued) pin symbol function configuration 100 ramp set 37 vs_mixer 42 gnd2 28 1k vs_if 33 rx_on tx_on 38, 39 5k 5k vs_if 33 gnd1 18 gnd2 28 270 270 mixer_out2 41 mixer_out1 40 gnd2 28 vs_mixer 42 vs_if 33
11 t2803 [preliminary] 4572g?dect?01/04 42 43 vs_mixer gnd_pll mixer supply voltage pll ground 44 ole open loop enable input 45 pu_rx/tx rx/tx power-up input pin description (continued) pin symbol function configuration gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 ole 44 5k 5k vs_pll 7 gnd_pll 43 pu_rx/tx 45 gnd18 18 25k 25k
12 t2803 [preliminary] 4572g?dect?01/04 46 pu_pll pll power-up input 47 tx_data tx data input of gaussian filter 48 i_cpsw charge-pump current control input pin description (continued) pin symbol function configuration pu pll 46 25k 25k 10k 10k 140k gnd pll 43 10k 20k 5k 5k vs_pll 7 tx_data 47 2.5k vs_pll 7 gnd_pll 43 i_cpsw 48 5k vs_pll 7 gnd_pll 43
13 t2803 [preliminary] 4572g?dect?01/04 functional description receiver the rf signal at rf_in is fed to an image rejection mixer ir_mixer with its differential outputs mixer_out1 and mixer_out2 driving an if-saw filter at 110.592 mhz or 112.32 mhz. the if_amp1 and if_amp2 if amplifiers with an external if_tank and an integrated rssi function feed the signal to the demodulator demod working at f=f if /2 ( 55 mhz) and finally to an integrated baseband filter bb. for demodulator tunning in production an integrated 5-bit digital-to-analog (d/a) converter is provided to control the on-chip varicap diode. transmitter the transmit data at tx_data is filtered by an integrated gaussian filter gf and fed to the fully integrated vco operating at twice the output frequency. after modulation the signal is frequency-divided by 2 and fed via a tx/rx switch to the tx_driver. this bus-controlled driver amplifier supplies typically +3 dbm output power at tx_out. a ramp-signal generator ramp_gen, providing a ramp signal at ramp_out for the external power amplifier, is integrated. the slope of the ramp signal is controlled by a capacitor at the ramp_set pin. synthesizer the ir_mixer, the tx_driver and the programmable counter pc are driven by the fully integrated vco (including on-chip inductors and varactors). the output signal is frequency-divided to supply the desired frequency to the tx_driver, 0/90 degree phase shifter for the ir_mixer and to be used by the pc for the phase detector pd (f pd = 1.728 mhz). open loop modulation is supported. power supply an integrated bandgap-stabilized voltage regulat or for use with an external low-cost pnp transistor is implemented. multiple power-down and current saving modes are provided.
14 t2803 [preliminary] 4572g?dect?01/04 figure 3. pll principle rf_in programable counter pc "- main counter mc "- swallow counter sc f vco = f pd x (s mc x 32 + s sc ) f vco phase frequency divider by 2 pa driver detector pd vco mixer vco dac f pd = 1.728 mhz gf_data gaussian filter gf reference counter rc 6.912 mhz ref_clk s rc 13.824 mhz 6 8 1.152 mbit/s pll reference tx_data frequency ref_clk baseband controller 10.368 mhz ext. loop filter charge pump
15 t2803 [preliminary] 4572g?dect?01/04 the following table shows the lo frequencies for rx and tx for the dect band plus additional channels for the extended dect band. intermediate frequencies of 110.592 mhz and 112.32 mhz are supported. table 2. lo frequencies formula tx: f ant = f vco = 864 khz (32 s mc + s sc ) rx: f ant = 864 khz (32 s mc + s sc ) + f if control signals table 3. control signals ? functions mode f if /mhz channel f ant /mhz f vco /mhz s mc s sc n tx ? c0 2401.056 2401.056 86 27 2779 c1 2401.920 2401.920 86 28 2780 ... ... ... ... ... ... c93 2481.408 2481.408 89 24 2872 c94 2482.272 2482.272 89 25 2873 rx 110.592 (for 10.368 mhz ref_clk recommended) c0 2401.056 2290.464 82 27 2651 c1 2401.920 2291.328 82 28 2652 ... ... ... ... ... ... c93 2481.408 2370.816 85 24 2744 c94 2482.272 2371.680 85 25 2745 rx 112.320 (for 13.824 mhz ref_clk recommended) c0 2401.056 2288.736 82 25 2649 c1 2401.920 2289.600 82 26 2650 ... ... ... ... ... ... c93 2481.408 2369.088 85 22 2742 c94 2482.272 2369.952 85 23 2743 signal functions i_cpsw charge pump current control pu_reg activates aux voltage regulator supplying the complete transceiver pu_rx/tx activates rx/tx blocks pu_pll activates pll circuits: pc, pd, cp, rc, vco rx_on activates rx circuits: bbf, demod, if amp, ir mixer tx_on activates tx circuits: tx-driver, ramp gen, starts ramp signal at ramp out ole activates open loop mode of the pll data word 1, bit d0 activates gf
16 t2803 [preliminary] 4572g?dect?01/04 table 4. control signals ? modes serial programming bus the transceiver is programmed by the 3-wire bus (clock, data and enable). after setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the msb-bit. when the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address bit condition (last bit). additional leading bits are ignored and there is no check made how many pulses arrived during enable low condition. during enable low condition, the bus current is increased to speed up the bus logic. the programming of the transceiver is separated into two data words. data word 1 con- trols mainly the channel information together with settings, which are closely related with the channel. data word 2 holds setup information, which is adjusted during production. modes tx mode rx mode rssi only pu_reg 1 1 1 pu_vco 111 pu_rx/tx 1 1 1 pu_pll 1 1 1 rx_on 011 tx_on 101 bb filter off on off demodulator off on off if amplifiers and rssi off on on ir mixer off on on rx switch off on on tx switch on off off tx driver on off off ramp generator on off off programmable counter on on on voltage-controlled oscillator on on on gaussian filter on off off phase detector/charge pump on on on reference counter on on on typical current consumption at v s = 3.2 v 56 ma 85 ma 82 ma
17 t2803 [preliminary] 4572g?dect?01/04 data word 1 d11 = x: do not care data word 2 e3, e4, e5 = x: do not care data word 1 programs pll settings with the reference counter bits d21 - d21 with the main counter bits d13 - d16 with the swallow counter bits d16 - d20 msb lsb data bits address bit d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a0 rc sc mc vs x 0 gfcs 0 000 cpcs gf 1 e12 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 a0 pa demoddac/rampdac x xx test 0 rc (reference counter) d22 s rc ref_clk 0 6 10.368 mhz 1 8 13.824 mhz mc (main counter) d16 d15 d14 d13 s mc 000080 000181 ... ... ... ... ... 111094 111195 sc (swallow counter) d21 d20 d19 d18 d17 s sc 000000 000011 000102 ... ... ... ... ... ... 1110129 1111030 1111131
18 t2803 [preliminary] 4572g?dect?01/04 vco selection with bit d12 gaussian filter on/off with bit d0 gf is used only in tx mode. gfcs adjustment with bits d7 - d9 only in tx mode effective for setting the frequency deviation of the modulation. cpcs adjustment with bits d1 - d2 used to adjust the charge pump current. this can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. vco selection d12 vco mode 0vco 1 1vco 2 d0 gf (gaussian filter) 0off 1on gfcs (gaussian filter settings) d9 d8 d7 gfcs 00060% 00170% 01080% 01190% 100100% 101110% 110120% 111130% cpcs (charge-pump current settings) d2 d1 cpcs 00-1 010 101 112
19 t2803 [preliminary] 4572g?dect?01/04 data word 2 programs demoddac adjustment with bits e6 - e10 only in rx mode effective. used to tune the demodulator center frequency and allows to compensate tolerances of external components and the t2803. rampdac adjustment for tx mode with bits e6 - e10 only in tx mode effective. used to control the power of the external pa by adjusting the ramping voltage. test mode settings with bits e0 - e2 in normal operation lock detect output is used. all other settings are for test only. demod dac voltage e10e9e8e7e6 f ifcenter % 00000 -5 00001 ... 00010 ... ... ... ... ... ... ... 11101 ... 11110 ... 11111 5 rampdac voltage (at pin 36 ramp_out) e10e9e8e7e6 v ramp_out 00000 1.1 v 00001 ... 00010 ... ... ... ... ... ... ... 10111 1.68 v 11000 1.7 v ... ... ... ... ... ... 11110 ... 11111 1.7 v e2 e1 e0 signal at lock detect output cp mode 0 0 0 lock detect active 0 0 1 pc out/2 active 0 1 0 rc out/2 active 0 1 1 do not care active 1 0 0 lock detect active 1 0 1 pc out/2 active 1 1 0 rc out/2 active 111 gftest: rcout active
20 t2803 [preliminary] 4572g?dect?01/04 output power settings with bits e11 - e12 use of maximum power (+3 dbm) for external pa is recommended. figure 4. 3-wire bus protocol timing diagram table 5. 3-wire bus protocol table figure 5. tx data timing pa (output power settings) e12 e11 pa 0 0 -21 dbm 01-11dbm 10-4dbm 11+3dbm data clock enable tt tec ts tc th tl tper 16525 description symbol minimum value unit clock period tper 125 ns set time data to clock ts 60 ns hold time data to clock th 60 ns clock pulse width tc 125 ns set time enable to clock tl 200 ns hold time enable to data tec 0 ns time between two protocols tt 250 ns refclk tx_data t s t h set-up time tx data ts > 8 ns when using refclk = 10.368 mhz, ts and th must be considered for falling and rising edge of refclk hold time tx data th > 8 ns
21 t2803 [preliminary] 4572g?dect?01/04 handling do not operate this part near strong electrostatic fields. this ic meets class 1 esd test requirement (hbm in accordance to eia/jesd22-a114-a (october 97) and class a esd test requirement (mm) in accordance to eia/jesd22-a115a. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . all voltages refer to gnd parameters pin symbol min. max. unit supply voltage regulator 10 v s_reg 3.2 4.7 v supply voltage 7, 12, 14, 33, 42 v s 3.0 4.7 v logic input voltage 1, 2, 3, 38, 39, 44-48 v in -0.3 v s v junction temperature t jmax 150 c storage temperature t stg -40 150 c thermal resistance parameters symbol value unit junction ambient r thja 25 k/w operating range parameters pin symbol min. typ. max. unit supply voltage regulator 10 v s_reg 3.2 3.6 4.6 v supply voltage 7, 14, 33, 42 v s 2.9 3.0 4.6 v supply voltage charge pump 12 v scp v s 4.6 v ambient temperature t amb -10 +60 c electrical characteristics test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit ir mixer (pins 29, 30, 40 and 41) input impedance pins 29 or 30 (single ended) z in 110 + j12 ? image rejection ratio pins 40 and 41 irr 20 db dsb noise figure pins 29 or 30 (single ended) nfdsb= nfssb 10 db conversion gain r load = 200 ? g conv 11 db input intercept point pins 29 or 30 (single ended) iip3 -7 dbm output impedance pin 40 and 41 (differential) z out 175 + j145 ?
22 t2803 [preliminary] 4572g?dect?01/04 if amplifier (pins 26, 27, 34 and 35) input impedance pins 34 and 35 (differential) z in 1200 - j480 ? lower cut-off frequency fl 3db 90 mhz upper cut-off frequency fu 3db 130 mhz power gain gp 85 db bandwidth of external tank circuit pins 26 and 27 bw3db 10 mhz noise figure nf 9 db rssi (pins 25, 34 and 35) rssi sensitivity at if_in1,2; pins 34 and 35 p min 20 dbv rssi compression at if_in1,2; pins 34 and 35 p max 100 dbv rssi dynamic range dr 80 db rssi resolution slope of the rssi has to be steady acc 2db rssi rise time p in = 30 to 100 dbv, pin 25 t r 1s rssi fall time p in = 100 to 30 dbv, pin 25 t f 1s quiescent output voltage at p in < 20 dbv at if_in1, if_in2, pin 25 v out 0.4 v maximum output voltage at p in = 100 dbv at if_in1, if_in2, pin 25 v out 1.9 v fm demodulator, bb-filter (pins 19, 20, 23 and 24) co-channel rejection ratio at p in = -75 dbm at ir-mixer input ccrr 10 db sensitivity quality factor of external tank circuit approximately 20, f res =f if /2, pin 24 s0.5v/mhz amplitude of recovered signal nominal deviation of signal 400khz, pin24 a 450 mvpp corner frequency pin 23: c = 68 pf f c 680 khz output voltage dc range pin 24 v outdc 1v s -1 v demod_dac range (see bus protocol e6 to e10) ? f ifcenter 5% vcos frequency range vco 1, d12 vs = 1 vco 2, d12 vs = 0 f vco f vco 2289 2289 2483 2483 mhz mhz tuning gain g tune 200 mhz/v frequency control voltage range pin 17 v tune 0.4 2.8 v pll scaling factor prescaler s psc 32/33 scaling factor main counter s mc 82 - 89 scaling factor swallow counter s sc 031 external reference input frequency ac coupled sinewave, pin 4 f ref_clk 10.368 13.824 mhz mhz external reference input voltage ac coupled sinewave, pin 4 v ref_clk 50 250 mv rms scaling factor reference counter s rc 6/8 electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit
23 t2803 [preliminary] 4572g?dect?01/04 charge pump (pin 13) output current v cp = v vs_cp /2, i_cpsw = ?1? pin 48 i cp_nom 7.5 ma output current v cp = v vs_cp /2, i_cpsw = ?0? pin 48 i cp_nom 1.2 ma current scaling i cp = i cp_nom + cpcs i cp_step (see bus protocol d1 ... d2) i cp_step 0.2 ma leakage current ole = ?1? i l 100 pa gaussian transmit filter (gaussian shape b t = 0.5) tx data rate 1152 kbit/s tx data filter clock 6 taps in filter f txfclk 6.912 mhz frequency deviation gf fm_nom 400 khz frequency deviation scaling gf fm = gf fm_nom gfcs (see bus protocol d7 ... d9) gfcs 60 130 % tx driver (pin 32) maximum output power at l = 5.6 nh, pin 32 (see bus protocol e11 - e12) p tx 3dbm minimum output power at l = 5.6 nh, pin 32 (see bus protocol e11 - e12) p tx -21 dbm rf leakage in rx mode p leak -47 dbm output impedance at l = 5.6 nh, 2.5 ghz, pin 32 z out 13+j40 ? ramp generator (pins 36 and 37) minimum output voltage v min 0.7 v maximum output voltage (see bus protocol e6 - e10) v max 1.1 1.8 v rise time c ramp = 270 pf at pin 37 t r 5s fall time c ramp = 270 pf at pin 37 t f 5s lock detect and test mode output (pin 5) lock detect output, test mode output locked = ?1?, unlocked = ?0? te s t m o d e s (see bus protocol e0 ... e2) ld leakage current v oh = 4.6 v i l 5a saturation voltage i ol = 0.5 ma v sl 0.4 v auxiliary regulator (pins 8, 9 and 10) output voltage v sreg = 3 v, pin 8 v reg 2.9 3.0 3.1 v vco regulator (pins 14, 15 and 12) output voltage v svco = 3 v, pin 15 v reg_vco 2.6 2.7 2.8 v 3-wire bus clock f clock 6.912 mhz logic input levels (clock, data, enable, rx_on, tx_on, ole, tx_data, data_hold) (pins 1, 2, 3, 38, 39, 44, 47 and 48) high input level = ?1? v ih 1.5 v low input level = ?0? v il 0.5 v electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit
24 t2803 [preliminary] 4572g?dect?01/04 high input current = ?1? i ih -5 5 a low input current = ?0? i il -5 5 a standby control (pins 6, 45 and 46) power up pu_reg = ?1? pu_rx/tx = ?1? pu_pll = ?1? high input level pin 6 pin 45 pin 46 v pu_reg v pu_rx/tx v pu_pll 2.0 v standby pu_reg = ?0? pu_rx/tx = ?0? pu_pll = ?0? low input level pin 6 pin 45 pin 46 v pu_reg,off v pu_rx/tx,off v pu_pll,off 0.7 v power up pu_reg = ?1? pu_rx/tx = ?1? pu_pll = ?1? high input current v pu = 3 v, pin 6 v pu = 4.6 v, pin 45 v pu = 3 v, pin 46 v pu = 4.6 v i pu_reg i pu_rx/tx i pu_pll 20 60 100 200 30 80 125 300 40 100 150 400 a a a a standby pu_xxxx = ?0? low input current v pu = 0 v, pin 6 v pu = 0.5 v, pins 45, 46 i pu,off 0.1 1 a a settling time v s = 0 active operation switched from v s = 0 to v s = 3v t soa < 10 s settling time standby active operation switched from pu = ?0? to pu = ?1? t ssa < 10 s settling time active operation standby switched from pu = ?1? to standby t sas < 2 s power supply (pins 7, 10, 12, 14, 33 and 42) total supply current rx i s 85 ma rssi only i s 82 ma tx i s 54 ma tx (gf active) i s 56 ma standby current pu_rx/tx = gnd i s 10 a supply current cp v vs_cp = 3 v, pll in lock condition, pin 13 i cp 1a electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit
25 t2803 [preliminary] 4572g?dect?01/04 figure 6. typical application circuit vcc bb_out rssi 48 i_cpsw 47 tx_data 46 pu_pll 45 pu_rx/tx 44 ole 43 gnd_pll 42 vs_mixer 41 mixer_out2 40 mixer_out1 39 tx_on 38 rx_on 37 ramp_set cp 13 vs_vco 14 vreg_vco 15 gnd_vco 16 vtune 17 gnd1 18 demod_tank1 19 demod_tank2 20 dac_dec 21 reg_dec 22 bb_cf 23 bb_out 24 1 2 v s _ c p 1 1 g n d _ c p 1 0 v s _ r e g 9 r e g _ c t r l 8 v r e g 7 v s _ p l l 6 p u _ r e g 5 l d 4 r e f _ c l o c k 3 e n a b l e 2 d a t a 1 c l o c k r s s i 2 5 i f _ t a n k 1 2 6 i f _ t a n k 2 2 7 g n d 2 2 8 r f _ i n 1 2 9 r f _ i n 2 3 0 g n d 3 3 1 t x _ o u t 3 2 v s _ i f 3 3 i f _ i n 1 3 4 i f _ i n 2 3 5 r a m p _ o u t 3 6 ole pu_rx/tx pu_pll tx_data i_cpsw tx_on rx_on ld pu_reg clock data enable ref_clk bc808 or similar 56 pf 220 pf 27 pf 27 pf 150 nh 47 pf 47 pf 180 nh 56 pf 470 nf 180 ? 150 nf 22 nf 68 pf 2.2 nf 100 pf tbd tbd 18 pf 100 nh tx_out rf_in saw filter tfs 112b tantal tantal 4.7 nf ramp_out 68 pf t2803
26 t2803 [preliminary] 4572g?dect?01/04 package information ordering information extended type number package remarks moq t2803-plq qfn48 taped and reeled 4000 pcs. T2803-PLS qfn48 tube 430 pcs.
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